Authored By:
Kevin J. Byrd, Brian Franco
Intel Corporation
Oregon, USA
Summary
The growing use of tin-bismuth (SnBi) based low temperature solder (LTS) in the electronics industry is driving increased research into how these metallurgies differ in behavior compared with Tin-Silver-Copper (SAC) solders. One area of interest is electromigration (EM). EM at the second-level interconnect (SLI) has not been a primary focus area for SAC-based systems. Bi, however, has higher mobility with current flow and thus understanding the risk for EM is valuable. There is a need to understand how electromigration may occur in systems and how best to select acceleration conditions to reduce time to data when assessing design risk. Significant work has been completed recently studying electromigration behavior in LTS-based assemblies using highly accelerated current density and ambient temperature conditions.
Given the relatively short history of LTS use for computers, very little data exists to document solder joint microstructure from functional systems with a known usage history. As a result, demonstrating that solder joint conditions post-acceleration meaningfully replicate actual solder joint conditions in the lifetime of interest is challenging. This paper will review a selection of previous results reported from accelerated testing. The results will be compared with cross-sectional results from components on functional systems with known time in service and current density/ambient conditions. Finally, additional areas for research will be noted and suggestions for design related methods for managing electromigration during system design will be proposed.
Conclusions
A significant amount of electromigration data reported in the literature has been based on eutectic SnBi solder. The use of eutectic SnBi allows results to be compared across both studies and solder paste suppliers. For actual electronic system designs, however, dopant modified paste metallurgies can provide enhanced margin against EM induced failures. When selecting an LTS solder paste, options employing Ag, Cu, Ni, and Sb can provide both EM benefits as well as improved thermal-mechanical performance. The functional systems evaluated in this work were assembled with LTS pastes using a selection of these dopants. While a paired comparison with SnBi is not possible, doped paste can be seen to have low risk of EM in an extended use case scenario. Products with lower Bi % are lower risk for EM, but offer less margin if hot tear elimination is required due to the higher peak reflow temperatures.
EM failure modes demonstrated in test vehicles such as lap shear joints, land grid array (LGA) sandwich solder joints, etc. can be recreated in functional notebook systems using similar accelerated current densities and temperatures. In the case of thin bottom terminated solder joints under accelerated conditions, localized melting and associated IMC growth, rather than EM driven Bi accumulation appears to be the dominant risk mode.
For production systems, knowledge of expected steady state current densities, motherboard temperatures, and likely use cases are key inputs for EM risk assessment. While design requirements will vary greatly, examination of post-service systems has shown that solder joint microstructure evolution may evolve rather slowly and EM related failure modes may not be a significant consideration.
Given the need for accurate data on expected current densities and solder joint temperatures in use case scenarios, it would be valuable to develop methods to quantify actual solder joint temperatures during operational cases rather than the chassis or global motherboard temperatures. As well, for high-risk components such as power FETS in higher temperature/current density applications, it will likely be necessary for component suppliers to develop solutions that allow current densities and solder joint temperatures to be more effectively managed.
Initially Published in the SMTA Proceedings
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