I'm concerned about voiding in the central ground planes of my QFN components. What can I do and how concerned should I be? Board Talk
Board Talk is presented by Phil Zarrow and Jim Hall of ITM Consulting.
Process Troubleshooting, Failure Analysis, Process Audits, Process Set-up CEM Selection/Qualification, SMT Training/Seminars, Legal Disputes
Phil Zarrow
With over 50 years experience in PCB assembly, Phil is one of the leading experts in SMT process failure analysis.
He has vast experience in SMT equipment, materials and processes.
Jim Hall
A Lean Six-Sigma Master Blackbelt, Jim has a wealth of knowledge in soldering, thermal technology, equipment and process basics.
He is a pioneer in the science of reflow.
Transcript
Phil
Welcome to Board Talk with Jim Hall and Phil Zarrow, the Assembly Brothers here at Board Talk, but by day going as ITM Consulting. And let's look at what kind of question we have today.
Jim
J.R. writes, "I'm getting concerned about voiding in the central ground planes of my QFN components. What can I do about that and how concerned should I be about it?"
First of all I want to say that although many of the components we deal with technically are QFNs, the new IPC term is BTC, Bottom Terminated Components.
Phil
So on these bottom terminated leadless components, sometimes known as QFNs, voiding issues have been around for a while. One question is how much voiding is actually permissible.That's defined by the conductivity and as well as the mechanical strength. We've seen cases where 65% voiding is permitted.
But if you want to try to reduce voiding there are a number of different methods. One methodology is the use of preforms. Indium Corporation has some excellent papers on this. The flux is on the outside of the preform, as opposed to mixed in with the solder paste in normal solder paste.
Jim
What does a preform look like?
Phil
The preforms we're talking about not the old-fashioned donuts we used to remember. These are basically solder slugs and they are introduced on tape in real and put down by the pick and place machines.
Jim
So it's a rectangular square piece of solid solder about the size or slightly smaller than the pad with flux on the outside.
Phil
So the flux has less chance to get entrapped as it might in solder paste. So that's a method worth experimenting with. Your result may vary, but it's well worth a try.
Jim
There are an infinite number of variations of the window pane technique where you print solder paste on less than a 100 percent of the area using some pattern of apertures within the standard within the area of the pad. That's a whole day's work, perhaps we will talk about that another day.
Phil
So thanks for listening. And whether you're soldering bottom terminated leadless components or big half-watt resistors, whatever you do ...
Jim
Don't solder like my brother.
Phil
Please don't solder like my brother.
Comments
Through our various studies on ground pad voiding, AIM discovered a no-cost, easily implemented stencil aperture design that can be consistently and repeatedly used to reduce void formation on QFN/BTC style packages. For AIM's detailed study, click the link https://aimsolder.com/technical-articles/aperture-design-minimize-qfn-voiding
Logan Jelinske, AIM Solder
Adjusting your reflow profile can be a tool to minimize voiding. The ultimate results have been found using a vacuum reflow oven.
Another effective method is increasing the time above liquidous. Entrapped vapor displays brownian motion in the molten solder joint. As voids reach the edge of the pad and escape, they can never come back.
A third technique which works with some paste chemistries is to keep the peak temperature below 240C. Some paste ingredients form gasses above 243C, eliminating this outgassing can reduce void area.
Mitch Holtzer, Alpha Assembly Solutions
Voiding occurs because the gases generated by the flux and other reactions, can not escape. In addition to everything already discussed, increasing the standoff height of the part can help. The methods I use is increasing the solder deposit length on the perimeter lands. As the solder reflows and pulls into the land area, it holds the part up higher, increasing the surface area of the sides of the center pad. This takes some analysis and DOE to get it right, but you can get the extra mil or two of height. This is also helps if you need to wash. The team over at Aim recently did a paper on this.
Alan Woodford, NeoTech
Lets not forget the interaction of the metallurgy involved here either.
Immersion gold PCBs will increase voiding particularly when used with some Lead Free solder pastes. This can be improved by using electroflash gold, or better yet convert to matte tin or silver finishes to reduce the variety of metals involved in the connection.
My experimentation has shown the Immersion gold finish makes it a challenge to do better than 50% void even with very good 12 zone reflow profiles.
In addition to electrical and mechanical reasons for limiting the amount of voiding, also need to consider how much voiding affects thermal conductivity for higher power applications.
Derek Vanditmars, Delta Controls
You talked about "How to Reduce Voiding on QFN Components, BTC. However, no comparison samples provided.
Victor G. Hernandez, Dell inc., USA
This is our longtime experience with good soldering results concerning central ground planes and exposed pads for QFNs/BTCs.
On design level we take:
for the copper pad: a 1:1 relation between the size of the central pad of the component and the pad size (X, Y)
for the solder paste : the 49% rule : size is (X * 0.70, Y * 0.70), centered within the copper pad.
For sizes > 4mm we draw manually solder paste dots in a way the total amount of solder paste is about 49% of the total copper pad area.
Take e.g. 1.4mm solder paste each 2.0mm Cu. Like this the flux fumes can easily get away.
Please don't put through hole via's inside such pads : control is lost over the amount of solder left, and, the other PCB side is getting influenced. Apply by preference copper filled microvias.
Patrick Hendrickx, Septentrio Satellite Navigation, Belgium
At a SMT table top show I attended in Austin, there was a talk about QFN/BTC components. Their rule was small holes in the ground plane and about 50% solder coverage. This became the 25% rule that we use. A strip 25% of the width and length of the ground pad is removed leaving a 4 pane solder pattern that is about 57% of the area. It works great for us in both leaded and lead-free solder applications.
