Authored By:
Satyajit Walwadkar, Reginald, Lai,Weston, Roth, Alexander Huettis, Samuel Oladji, Juan Landeros, Behrooz Shamsodini , Srinivasa Aravamudhan
Intel Corporation
OR, USA
Summary
Printed circuit boards (PCB) are considered as the backbone of today’s modern electronic devices. PCBs are comprised of alternate layers of conductive and insulating material and serve as a foundational building block for most devices. Electrical interconnects in PCBs are developed by stacking and laminating multiple tightly spaced interconnected conductive layers to form a multi-layer PCB. Manufacturing of a multilayer PCB is complex and involves lamination, drilling and outer layer finishing processes. A typical, type 4 multi-layer PCB undergoes multiple lamination cycles in comparison to a relatively less complex type 3 multi-layer PCB which only needs a single lamination cycle. A limited understanding exists of the impact of the PCB lamination process on PCB ball grid array (BGA) land pattern warpage and surface mount technology (SMT) yield.
This paper discusses the influence of the PCB design parameters, PCB materials, and PCB lamination process on PCB warpage. Both thick and thin PCB cases are presented to capture manufacturing process variability on Type 3 and Type 4 PCBs. Non-destructive metrology was used to quantify and establish incoming PCB land pattern warpage window. SMT yield performance of a BGA package under low temperature solder (LTS) assembly conditions are evaluated on these PCBs to validate incoming PCB land pattern warpage window and to develop a strong understanding of PCB lamination process impact. Finally, recommendations are provided on PCB designs, material selection, and manufacturing optimization to help reduce PCB warpage and maximize SMT Yield.
Conclusions
As technology continues to scale, understanding and controlling PCB BGA land pattern warpage is critical to achieve high SMT yields. Findings from this work have highlighted 3 vectors namely PCB copper layer pair balance, PCB material selection, and PCB lamination process optimization as the key knobs to minimize and control PCB BGA land pattern warpage. Below are the summarized recommendations.
Control PCB layer pair copper density balancing to less than 10% as a design parameter to better balance PCB designs. Both thick and thin PCBs manufactured using single and multi-lamination processes have shown to benefit from this design recommendation in keeping warpage variability under control. Balanced PCB designs show less variation in incoming PCB BGA land pattern warpage. Additionally, the methodology adopted for SMT cliff assessment at different warpage levels has shown to quickly highlight any SMT issues due to excessive PCB BGA land pattern warpage.
Proper PCB material selection has aided in meeting electrical requirements at low warpage levels. Thick PCBs with specific high-speed requirements have benefited from a hybrid material stack construction. Better flow ability of a standard prepreg material during lamination process is shown to aid in reducing PCB BGA land pattern warpage on a hybrid material stack.
The lamination process has the biggest impact on the PCB BGA land pattern warpage. Thick PCB designs (Type 3) manufactured using a single lamination process show high warpage variability mainly due to the configuration within a book structure. Book lagging structure adjustments in conjunction with surface deformation characterization offer benefits in developing an optimized lamination process recipe for better warpage control. Thin PCB designs (Type 4) subjected to a multi-lamination process show comparatively less sensitivity to a book structure.
Initially Published in the SMTA Proceedings
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