Authored By:
Samuel Z. Grosso, J. Elliott Fowler, Ph.D, Matt A. Kottwitz, Ph.D, John Williard
Sandia National Laboratories
NM, USA
Summary
As electronics continue to decrease in size, dendrite growth is a growing concern for long term reliability of printed circuit boards (PCBs). Dendritic growth is a process that is caused by electrochemical migration (ECM). When the metal of the anode reacts with contaminants in the air or on the surface of the board, they form ions, which follow the path of the electric field. The metal from the anode begins to bridge the gap to the cathode, as the migrating ions follow the shortest path and deposit on the tip of the forming dendrite. If the dendrite structure reaches the cathode, a short occurs, and results in a temporary failure for the PCB.
In past literature, the relationship between voltage bias and the tendency (propensity) of dendrites to form has been inverse; as the voltage bias increases, different failure mechanisms, such as dielectric breakdown, dominate and do not allow dendritic growth to occur. In this study, we analyzed the effect that voltage bias has on dendrite growth both in clean PCBs and PCBs that were contaminated. All boards were first cleaned thoroughly in-house, to set a baseline.
The boards were contaminated with different concentrations of chloride-containing salts, then imaged at 30x magnification. The boards then were inserted into the SIR chamber, with environmental conditions set to 90% RH and 40C. The boards rested overnight to stabilize, and then a bias voltage was applied. The time between measurements was set to 5 minutes, for 168 hours of total test length. The surface insulation resistance graphs of these boards served as an indicator of any electrochemical processes that occurred during the test. The boards then were re-imaged at 30x magnification, and any areas of interest were looked at with the DSC for further evaluation.
Conclusions
The experimental design was performed with no incidents. The boards were given appropriate time to adjust to the new temperature before the humidity was increased, and there was no evidence of excessive condensation before the experiment began. Likewise, the roof of the chamber was examined after all experiments, and there was no evidence of water condensation that could have dripped onto the PCBs that were being tested. Results in Figures 1 and 2 were obtained, for both the masked/ENIG plated PCBs.
The SIR graphs for clean, masked, ENIG plated boards were consistent, despite the increase in voltage bias, as shown in Figures 1 and 2. All graphs demonstrated what appears to be an exponential decay in resistance over the period of the test, which levels out at similar resistance values which are well above the threshold for acceptable. One channel experienced a failure about 120 hours in, however analysis under SEM and EDS determined that it was not due to electrochemical migration.
The SIR for contaminated, ENIG plated PCBs with solder mask demonstrated differing characteristics with varying bias voltage. In all contaminated experiments, the SIR begins at a lower value, and resistance increases linearly with time (remember these are plotted on a log10 scale) for the transient portion of the graph. At the end of the transient period, the resistance stops increasing at its linear rate, and in some cases begins decreasing. The initial SIR reading of these PCBs increases as the voltage bias increases. At 5V, the initial resistance was 6.9E6 ohms; at 10V 9.4E7 ohms; and at 25V 1.6E10 ohms.
The time to reach the stable period also decreases as voltage bias increases. There are multiple failures of contaminated PCBs, and the occurrence of failures that were caused by ECM increased as the bias voltage increased as well. These results are shown in Table 1.
Initially Published in the SMTA Proceedings
|
