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Limitations of ROSE Testing Versus Localized Contamination
Board Talk
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TranscriptPhil And welcome to Board Talk with Jim Hall and Phil Zarrow, the Assembly Brothers, who by day go as ITM Consulting. We are here to talk to you about electronic assembly, process, problems, situations, everything under the sun that you may bring up to us. We welcome your questions. Jim, today we have a question from W.H. It is a cleaning question, which is good because we are doing this broadcast from the ITM cleaning closet. W.H. says, I am glad that the industry is finally recognizing the limitations of ROSE testing versus localized contamination. But what can I use instead to validate the cleanliness of my finished product? Wow, what a great question. Jim, I know how fond you are of the ROSE process, so let it rip. Jim The ROSE process has been in question for many years. The basic problem is its inability to identify small amounts of localized contamination. Principally because at the end of the ROSE test you take whatever contamination was measured and you average it over the whole surface of the entire circuit board. If you have one small component, like a BTC, QFN, that has trapped some bad chemicals under there because it didn’t get washed or heated properly and you dump it in a ROSE test, even if the alcohol and water is successful in getting under that component, dissolving all of that contamination and measuring it accurately, it then takes that contamination that is in maybe a quarter square inch of the surface and averages it over your whole circuit board. You typically come up with a value of cleanliness that is acceptable. But you have that one little time bomb sitting there waiting for you. The IPC and everyone else have finally realized this and saying no, we can’t use this for definitive testing and qualification of our processes, either no-clean or cleaning. Phil Alternative methods for checking cleanliness have been. Jim First off, inspection. If you can look at the surfaces, that is a simple, crude way of doing it. For process development, we always used to pry some components off the board and just look to see what was under there. That is a destructive test. It isn’t quantitative, it is qualitative. Phil We have ion chromatography, or IC as we like to call it. This is a good methodology. However, there is no panacea test. It definitely has its advantages. It does give us a level. Then we have very localized ion chromatography or C3, which is the Foresite process. These are very good. But we see them mostly advantageous, for qualifying a process, but generally they are really advantageous in doing failure analysis, particularly C3. So, what has the IPC adopted? Basically, the direction they have gone to and are formalizing is surface insulation resistance testing or SIR testing. One of the problems with SIR testing is that it requires that little SIR comb pattern to be on the board, whether its on the board itself or a component or wherever we are testing. Then of course the resistance of the residue across the surface of that is measured and this is typically in the megohm range. That’s good but the other situation here is to do with static, you reflow it and see what it is like. After all the board is going to living in an environment and one of the things we are concerned about, particularly when we are talking about no-clean, is how is that residue reacting with the ambient atmosphere. Obviously, we can’t have too volatile an atmosphere in terms of humidity or no-clean would not be the answer here. Where we are using it is in an environment, or if we are cleaning a no-clean for various reasons, we want to know just how well we have done that. We have certain values, in terms of SIR, and the methodology that has emerged that we find is a really good solution is what we call dynamic SIR testing. Here the boards are prepared usually with test coupons and then they are subjected to a humidity change, 50% relative humidity for a period of about 100 hours more or less. It is basically track lock in terms of the SIR values. Usually, you want to see something above lock 8 to be acceptable. Some places might have more stringent standards. This is a methodology that is emerging. SIR is being adapted as a standard. We recently used for risk assessment and risk management, going to a no-clean process was using this SIR, what I call dynamic SIR testing. We used the facilities of Manalytix in Nashville Tennessee. They have done some really good pioneering work in this methodology. Again, having just gone through a no-clean process qualification and risk assessment, risk management with certainly made a believer out of me and dynamic SIR testing. Jim, do you have anything you want to add to that? Jim No, just that it allows you to create SIR test patterns right under simulated real components. Whereas traditional IR tests have been these sample boards with these big comb patterns, but they aren’t really completely representative of the boards you are building. This way you can actually test the SIR and the physical configuration and the actual assembly process that you are using. You are really qualifying your process and validating it. Phil Right, now in this particularly case in this recent project we did with Manalytix, they prepared coupons of both surface mount components, QFNs, and also with through-hole components that were used in wave soldering, selective soldering, and with selective aperture pallets for wave soldering and also the through-hole world for repair and rework. They were able to test all of those processes and qualify the CEMs for our client to be able to do that. We were able to do that with the dynamic SIR testing. It is a good methodology and I think you are going to see it really catching on. I would say like wildfire but we are dealing with cleaning here. Hopefully we answered W.H.’s questions and educated everybody else. We look forward to your comments and further questions and elaborations. Thank you for listening to Board Talk today with Phil and Jim. Remember, whether you are going to clean your boards or not and whatever residue might be on them, whatever you do don’t solder like my brother. Jim And don’t solder like my brother. |
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