Authored By:
Mike Vinson, Averatek, Santa Clara, CA
Summary
The need for increasingly complex electronics combined with the obsolescence of larger component packages is driving innovation to provide alternatives to the traditional subtractive-etch fabrication process to reliably and repeatedly provide circuit layers with 25 micron or finer feature size. Liquid Metal Ink (LMI™) technology is one of those innovations.
LMI™ allows a very dense thin catalytic seed layer which results in a very dense thin electroless copper layer that can then be used as a base for a much thicker electrolytic copper layer. Because the electroless copper can be so thin (0.1 µm) compared to the electrolytic copper (> 10um) very fine geometries can be defined with a simple flash etching process without risking undercutting the traces. This is the core technology that allows Averatek’s Semi-Additive Process (A-SAP™) to realize very fine feature sizes.
This process is compatible with most printed circuit board (PCB) processes and utilizes conventional PCB equipment. The resulting circuit features can resolve to 25 microns or below, providing a cost-effective solution to complex routing constraints that currently result in multiple lamination, stacked and staggered micro via solutions. LMI™ enables the mixing of a subtractive process with advanced processes such as A-SAP™ in several different ways. This mix and match approach can be used to build a Substrate Like PCB (SLP) and these combinations expand the practicality and performance of the circuit. These very high-density circuit layers can stand alone or can be combined with layers created by the subtractive etch process that do not require such fine pitch. This combination efficiently results in the reduction of total number of layers and lamination cycles.
A higher manufacturing feasibility results from selecting the best manufacturing methodologies for each portion of the target system. This unique ability to combine standard and advanced processes will leverage the current domestic manufacturing infrastructure while extending capabilities well beyond the next generation interconnect.
Conclusions
Subtractive methods where foil is etched away to form circuits are established processes that will continue for quite some time into the future but uses for this technique will be limited in the fast-growing High-Density Interconnect (HDI) market. A new leapfrog technology, A-SAP™, is available to accelerate the adaptation HDI solutions through efficient methods and materials, requiring minimal investment in readily available equipment.
Some markets such as substrates for ICs can tolerate the higher costs typically associated with mSAP. The commercial-volume scale of smartphones and other system level PCB manufacturing is far less forgiving where costs and production efficiencies are concerned.
Initially Published in the SMTA Proceedings
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