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Selective Soldering Design for Reliability Using a Novel Test Board and SIR Test Method
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Authored By:Mike Bixenman and David Lober KYZEN Corporation TN, USA Mark McMeen STI Electronics Denis Jean KESTER Inc. Joe Clure KURTZ ERSA SummaryThe reliability of selectively soldered PCBs is a product of a complex interaction of several factors determined by the PCB design layout, flux, selective soldering machine, cleanliness, and end-user environment. Selective solder flux must be present and active to achieve reliable solder connections. The precision of flux transferred to the soldering area is critical to prevent leakage currents and dendritic growth on products used in harsh operating environments. Surface Insulation Resistance (SIR) is an effective method for predicting long-term failure mechanisms and as a predictive tool for service life reliability. SIR is a quantitative test method to evaluate electrochemical reactions from ionic contamination following the selective soldering process. A custom designed mixed technology test board, used for this study, has a connector next to surface mount components. The reliability of the soldering process will be tested using SIR IPC-TM 2.3.7 test method. The purpose of this research is to develop a test method designed to evaluate the electrochemical reliability of the selective soldering process at the assembly site. We will examine the impact of four (4) solder fluxes for flux spread and tackiness. Following these tests, the boards will be SIR tested at 40°C, 85% RH for 168 hours. ConclusionsOEMs, CMs, and Assemblers find need to evaluate material and process changes on their circuit card assemblies. There is also the need for improved test methods that can be used at the assembly site for system design, process development, process control, and quality assurance. Surface Insulation Resistance testing is an effective method for incoming inspection, materials investigations and qualifications, quality conformance, prediction of long-term failure mechanisms and as a predictive tool for estimated surface life. It is essential that the test boards be processed under a set of typical manufacturing conditions. The test board design for this research used a highly dense layout for both the connector and SMT components. The board layout included line spacing, physical geometry of the test patterns, routing of the lands from test patterns to contact fingers, physical spacing of voltage application lines and current return lines, the physical size of the test board, the presence of guard traces, and surface topography of the laminate. The testboard was effective at performing materials evaluations on selective soldered boards. Initially Published in the SMTA Proceedings |
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