Authored By:
Mustafa Ozkok, Sven Lamprecht, Akif Ozkok, Dolly Akingbohungbe, Moody Dreiza
Atotech Deutschland GmbH
Berlin, Germany
Alex Stepinski
GreenSource Fabrication LLC
Charlestown, NH, USA
Summary
The electronics industry is further progressing in terms of smaller, faster, smarter and more efficient electronic devices. This continuous evolving environment caused the development on various electrolytic copper processes for different applications over the past several decades.
There are 4 main drivers which forced the chemical supply industry to introduce new electrolytic copper processes with the new feature of "filling" capability over the years. The 1st driver is the continuous miniaturization of electronics. The first blind microvias were introduced with HDI technology in the late 1980s and early 1990s. In 1996, the IC Substrate market started to fill the micro vias. "Plugging" technologies were introduced in order to stack the micro vias to save space or to create "via in Pad" structures. This "plugging" technology with conductive paste was very expensive because of the additional process steps required.
Today copper filled microvias are the standard for almost all HDI PCB manufacturers. The 2nd driver is the thermal management on a substrate. Solutions were needed to integrate features with high thermal conductivity to manage the heat transfer on the substrates from one side to the other in order to minimize hot spots on the electronic devices over a lifetime. The higher the chip performance is, the more it tends to generate local heat-spots resulting in an early loss of the electronics in the field. The reason for this is the degeneration of various materials at these local hot spots.
Meanwhile the complete copper filled through holes was realized in 2006, by bridge plating or X -plating technology. Nowadays, completely copper filled through hole structures are at the leading edge of technology for thermal via structures because copper has almost the best thermal conductivity and it has to be plated nonetheless. The 3rd driver is the signal frequency. Electronic signals in an electronic package or inside of a PCB are increasing over time and continue to do so. Stacked microvias and fan-out vias are becoming more and more of a disadvantage for the transmission of high frequency signals, due to the fact of creating resistances at high frequencies. Therefore, the push of high frequency applications further increased the demand for technologies like copper filled through holes.
The 4th driver especially for through hole filling, is the quality-yield aspect. The alternatives for electroplated copper filled through holes, requires many additional process steps, or new materials such as plugging pastes. Each of these additional process steps or materials introduces a variety of risks and manufacturing problems resulting in lower yield.
Therefore the "one step" solution to fill through holes with copper is the preferred solution, without introducing new materials into the PCB. This paper describes the reasons for development and a roadmap of dimensions for copper filled through holes, microvias and other copper plated structures on PCBs. The paper will contain aspect ratios, dimensions and results of plated through holes used today in high volume manufacturing for microvia and through hole filling with electroplated copper. Furthermore, it will also show feasibility studies of new electroplated structures for future applications such as copper pillar plating on IC-substrates.
Conclusions
This paper presents the actual status of microvia filling and through hole filling realized by electrolytic copper plating processes. The dimensions of microvias and through holes which can be filled by electrolytic copper processes today are shown. Furthermore, the copper filling technologies versus paste plugging were compared and the benefits of the copper filling technologies have been illustrated. The scope of future developments in terms of microvia filling and through hole filling have been addressed. Next generation technology segments such as Panel Level Packaging (PLP) and also plating of copper pillars on IC Substrates, realized by a novel electrolytic copper plating processes were also considered.
Initially Published in the SMTA Proceedings
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