Authored By:
Lauren Cummings and Priyanka Dobriyal, Ph.D.
Intel Corporation
Hillsboro, OR, USA
Summary
With increasing consumer demand for smart phones, wearable devices, and Internet of Things applications, there is a growing trend in package and printed circuit board (PCB) miniaturization. In particular, wafer-level packages (WLPs) have garnered recent popularity for their affordable cost, small footprint, and thin profile. Component suppliers must be prepared to support failure analysis (FA) for PCBassembled WLPs, including fault isolation (FI), nondestructive screening, as well as destructive analysis techniques. If a board- or package-level failure is subtle or cannot be detected non-destructively, the WLP requires rework and reball before proceeding with further component-level testing and destructive FA. Due to their fragility and small form factor, the rework and reball process steps pose considerable risks for WLPs.
The component lacks a package substrate and is easily damaged using traditional rework tooling and handling. On highdensity boards and modules, there is also a risk for adjacent board-side passives or packages to be bumped and damaged during package removal from the PCB. The present work addresses the rework and reball challenges of a specific WLP case study, and suggests improvements for maintaining the true failure signature. Rework and reball recipes were successfully developed for a WLP, and optical microscopy (OM) and C-mode scanning acoustic microscopy (CSAM) were used to inspect for thermally or mechanically-induced artifacts. By implementing enhanced WLP rework and reball methods, the industry will be better poised to improve the quality and reliability of small form factor devices.
Conclusions
Rework and reball recipes were successfully developed for board-assembled WLPs. OM and CSAM inspection were erformed in order to evaluate the rework and reball process yield, and screen for thermally or mechanically-induced artifacts. The risk for mechanical damage was minimized by thermally demounting the WLPs with a vacuum pick-up tube and soft vacuum cup. Temperature was well-controlled using a no-contact vacuum scavenge technique to desolder the package. Lastly, the WLPs were reballed using a solder preform and a small metal weight. CSAM and OM did not reveal any thermal artifacts during the rework process, but chipping artifacts were found on the backside protection tape and near the dielectric and top layer metallization. WLPs with frontside chips failed subsequent componentlevel testing, showing that small dielectric and metal defects can sacrifice electrical functionality. Both backside and frontside chipping artifacts were successfully eliminated by improving handling and storage techniques. By implementing similar rework and reball improvements, the industry will be prepared to support WLP FA while maintaining the true defect signature.
Initially Published in the SMTA Proceedings
|
