Authored By:
Subramanian R Gowthaman, B.E., Unique Rahangdale, B.E., and DerejeAgonafer, Ph.D.
The University of Texas at Arlington
Arlington, TX, USA
Summary
Today, there is a revolution in going for miniaturization in size of electronic packages. More thinner, lighter and complex packages are in use for almost every electronic device. This initiation was taken to the next level and gives us a whole new ideology called 3D packaging. Currently, 3D packaging is the on-going research in almost all the electronic packaging related industries. 3D package uses Through Silicon Via (TSV) technology that gained momentum in the development and helped packaging system for significant miniaturization and power reduction, which result in increased performance. However, the reliability assessment is needed to evaluate the critical areas in TSV based 3D ICs. In electronic packages, reliability is the most important issue for electronic device manufacturing company and in any research institutes.
In this paper, the different types of crack that can happen along the TSV/Si interface has been determined with the study of behaviors of crack. Finite element method is used for the analysis of TSV region and calculation of stress intensity factor (SIF). Stress Intensity Factor (SIF) is a function of applied load, component dimensions and the length of the crack. Analyzing all these functions will help us to give more ideas about crack propagation and thereby help us to take preventive measures.
TSV structure contain silicon and copper which develop stress intensity factor. Comparison of fracture toughness of silicon and developed stress intensity factor is made. Finite element analysis is done to calculate stress analysis due to mechanical effect under reflow conditions, which is important for material characterization, TSV geometry, etc. Interfacial delamination of TSVs may encounter large stress because of the shear stresses that develops at the interface. This creates a relation between crack growth and SIF at the interface. Also the relation between geometry of the package and the crack growth is finally analyzed.
Conclusions
The variation of radial crack or crack propagation along the length of the silicon die has been successfully studied, through the TSV passage. The crack is modeled successfully and checked for different dimensions of crack. The cut boundary condition from the global model and sub model where used for simulation. The variation of J-integral value is used in calculating strain energy release rate per unit fracture surface and is determined with respect to crack size, die - substrate thickness and length of crack. The variation of crack length and size has also been successfully leveraged to investigate its effect on stress distribution and found that it is directly proportional to J-integral, whereas the relation between J-integral and die-substrate thickness shows an inversely proportional relational property up to certain limit of thickness
Initially Published in the SMTA Proceedings
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