Authored By:
Craig Hillman, Nathan Blattau, DfR Solutions, Beltsville, MD
Matt Lacy, Advanced Energy Industries, Fort Collins, CO
Summary
Solder joint reliability of SMT components connected to printed circuit boards is well documented. However, much of the testing and data is related to high-strain energy thermal cycling experiments relevant to product qualification testing (i.e., -55C to 125C). Relatively little information is available on low-strain, high-cycle fatigue behavior of solder joints, even though this is increasingly common in a number of applications due to energy savings sleep mode, high variation in bandwidth usage and computational requirements, and normal operational profiles in a number of power supply applications.
In this paper, 2512 chip resistors were subjected to a high (>50,000) number of short duration (<10 min) power cycles. Environmental conditions and relevant material properties were documented and the information was inputted into a number of published solder joint fatigue models. The requirements of each model, its approach (crack growth or damage accumulation) and its relevance to high cycle fatigue are discussed. Predicted cycles to failure are compared to test results as well as warranty information from fielded product. Failure modes were confirmed through cross-sectioning.
Results were used to evaluate if failures during accelerated reliability testing indicate a high risk of failures to units in the field. Potential design changes are evaluated to quantify the change in expected life of the solder joint.
Conclusions
A strain energy based first order model is capable of relatively accurate prediction out to 50,000 power cycles with dwell times less than 5 minutes. This would suggest that plastic strain and creep continue to play a critical role in solder joint fatigue even under conditions that would tend to be extended beyond typical low-cycle fatigue.
Initially Published in the IPC Proceedings
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